1. Field of the Invention
This invention relates to computer systems, and more particularly, to methods and apparatus for preventing the over-erasure of individual flash electrically-erasable programmable read only memory (EEPROM) devices in an arrangement including a plurality of arrays of such devices.
2. History of the Prior Art
Flash EEPROM devices are being used for many purposes in present day digital circuits such as computers because of their ability to retain data when power is removed and to be easily reprogrammed. A flash EEPROM memory array is comprised of floating gate field effect transistor devices. By programming, the charge stored on the floating gate of such memory transistors may be changed, and the condition (programmed or erased) may be detected by sensing the devices (cells). Because of their usefulness, flash EEPROM devices are even being used as substitutes for long term memory such as electro-magnetic disk drives. Such an array provides a smaller lighter functional equivalent of a hard disk drive which operates more rapidly and is not as sensitive to physical damage. Such memory arrays are especially useful in portable computers where space is at a premium and weight is important.
Flash EEPROM memory arrays do exhibit problems, however. One such problem which has been discovered is that they can be over-erased, a condition in which the devices cannot be shut off with conventional drive signals. The conventional method of erasing an array of N type flash EEPROM memory cells erases some large block of the cells together. Typically, this requires the application of twelve volts to the source terminals of all of the memory cells in the block, while grounding the gate terminals and floating the drain terminals. A N type flash EEPROM device which has been erased has few electrons on the floating gate, has a low threshold voltage Vt, and consequently transfers current when a relatively low level of gate voltage (e.g., 2-3 volts) is applied. If a device has been over-erased, however, even application of a zero voltage level at the gate terminal may be insufficient to stop current flow. Devices which cannot be shut off can in conventional memory arrangements, cause the memory array to provide incorrect output data when sensed.
When a very large number of flash EEPROM devices are utilized as in a long term memory array meant to supplant an electro-magnetic hard disk drive, then circuitry may be provided for assuring that over-erasing does not occur. Typically this circuitry is complex and requires a substantial amount of die space. For example, some flash memory arrays utilize very complicated state machines to control all aspects of programing and erasing the flash EEPROM devices so that each of these operations is very precisely controlled.
There are may arrangements using smaller flash EEPROM memory arrays with which it is not economically feasible to provide the circuitry used with large long term flash EEPROM memory arrays to assure that over-erasing does not occur. For example, field programmable gate arrays may utilize a number of small flash EEPROM memory arrays to provide initial conditions which define the logic operations provided by such gate arrays. Usually, these flash EEPROM memory arrays are programmed and erased by a user only when setting up the initial conditions or when providing new initial conditions, very infrequently occurring operations; and the initial conditions which are set up usually remain constant once the array goes into use, typically for the life of the part. Since the states of these flash EEPROM devices are normally changed so infrequently, it is not feasible to provide circuitry for precluding over-erasing which may occur only a few times in the life of the device. On the other hand, in arrangements including a large number of small flash EEPROM memory arrays, the physical structure of the devices from one flash EEPROM memory array to the next is likely to vary sufficiently that over-erasing of devices in some arrays may occur while devices in other arrays are still erasing. Moreover, the propensity of users to over-erase flash EEPROM arrays seems to be much greater than might be expected. It is, therefore, desirable to provide arrangements for protecting against over-erasing devices in flash EEPROM memory arrays where the typical circuitry protecting against such over-erasing is not available.